M. Mastella, MSc

M. Mastella, MSc
E-mail:
m.mastella rug.nl

Research

Publications
  1. Tunneling-based CMOS Floating Gate Synapse for Low Power Spike Timing Dependent Plasticity

    Mastella, M., Toso, F., Sciortino, G., Prati, E. & Ferrari, G., Aug-2020, Proceedings - 2020 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020. Institute of Electrical and Electronics Engineers Inc., p. 213-217 5 p. 9073965. (Proceedings - 2020 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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