Colloquium Computer Science - Dr. L. Bagheriye
|When:||Mo 28-09-2020 14:20 - 15:05|
|Where:||online (via BlueJeans)|
Title: Neuromorphic computing: Designing across the device-circuit-architecture-algorithm stack
To explain the design and requirements of the Neuromorphic computing paradigm we need to know about hardware, algorithm and computer architecture design. To this end, I will go through my research background in three different sections. In section I, for device-circuit part, the technology level design such as FinFET, CMOS and Non-volatile (NV) devices for memory arrays will be explained; then NV-SRAM cells for dynamically reconfigurable FPGAs with NV devices as well as a high speed, high sensing margin read circuit for STT-MRAMS will be discussed. In section II, for machine learning part and system level design, conducted research on Machine learning/statistical based approach for On-chip prognostics of dependable MP-SoCs by data driven approaches in a multi-sensory platform (Embedded instruments) will be presented. Moreover, finding the most representative critical paths of an open core processor due to dependability issues by different algorithms will be explained. Finally, in section III, Neuromorphic computing paradigm as energy efficient computing via spiking neural networks (SNN), third generation of neural networks and their implementation in Loihi Processor and memristive crossbar arrays will be discussed.