A Multichip Pulse-Based Neuromorphic Infrastructure and Its Application to a Model of Orientation SelectivityChicca, E., Whatley, A. M., Lichtsteiner, P., Dante, V., Delbruck, T., Del Giudice, P., Douglas, R. J. & Indiveri, G., May-2007, In : IEEE Transactions on Circuits and Systems I - Regular papers. 54, 5, p. 981-993 13 p.
Research output: Contribution to journal › Article › Academic › peer-review
The growing interest in pulse-mode processing by neural networks is encouraging the development of hardware implementations of massively parallel networks of integrate-and-fire neurons distributed over multiple chips. Address-event representation (AER) has long been considered a convenient transmission protocol for spike based neuromorphic devices. One missing, long-needed feature of AER-based systems is the ability to acquire data from complex neuromorphic systems and to stimulate them using suitable data. We have implemented a general-purpose solution in the form of a peripheral component interconnect (PCI) board (the PCI-AER board) supported by software. We describe the main characteristics of the PCI-AER board, and of the related supporting software. To show the functionality of the PCI-AER infrastructure we demonstrate a reconfigurable multichip neuromorphic system for feature selectivity which models orientation tuning properties of cortical neurons.
|Number of pages||13|
|Journal||IEEE Transactions on Circuits and Systems I - Regular papers|
|Publication status||Published - May-2007|
- address event representation (AER), asynchronous, cooperative-competitive, neural chips, neural networks, neuromorphic, orientation tuning, peripheral component interconnect (PCI)-AER, VLSI, winner take all (WTA), VISUAL-CORTEX, ARCHITECTURE, MECHANISMS, SYNAPSES, NETWORK, NEURONS